Cache memory may be utilized by processors or processing cores for fast access of contents stored in (slower) system main memory. Caches may be hierarchically organized into multiple levels, e.g., include a Level 1 cache (L1), Level 2 cache (L2) and so on. Typically, in a multi-level cache environment, all the data stored in a low level cache is also present in a higher level cache. For example, all data in the (low level) L1 caches are present in the (higher level) L2 cache that the L1s share.
Advances in memory device technology have allowed for increasingly large caches to be used for higher level caches. If efficiently exploited, a large cache may be of utmost importance by significantly reducing the miss rates and on-chip/off-chip bandwidth requirements, in turn improving overall system performance and cost.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.